1. Field of the Invention
The present invention generally relates to means for electrically interconnecting multilayer substrates and, more particularly, to a carrier board for pinless connectors interposed between multilayer substrates and a circuit board for making electrical connections therebetween.
2. Description of the Prior Art
Electrical interconnections for stacked circuit boards have been extensively used in the prior art, but in each instance they seem to fall short of providing the reliability required in the computer industry. For instance, U.S. Pat. No. 4,793,814 to Zifeak et al. describes an electrically nonconductive support member for holding a plurality of electrically conductive interconnect elements for electrically interconnecting stacked circuit boards. This technique is quite effective in theory, but it has several inherent problems, the first being that during the fabrication of the interconnector board, the electrically conductive connectors are inserted through the elastomeric foam carrier and then the elastomeric material is allowed to set. Upon assembling and compressing the circuit boards and interconnector stack, the contacts make intimate contact with the electrical pads on the circuit boards, ceramic boards/cards and other products, and during the compression and contact wipe action, the respective ends of the interconnectors are essentially buried in the foam carrier, which makes for less pressure between the pads and the respective ends of the connectors, thereby effecting an insecure connection between the interconnector and circuit board pads. Another glaring problem occurs when a poor contact is formed between an interconnector and the circuit, requiring a replacement of the interconnector. In structure described in the Zifeak et al. patent, the entire interconnection carrier, with new interconnectors, must be replaced, instead of the single interconnector, and this is both time consuming, expensive and functionally inferior.
Other circuit interconnection techniques have also been used, such as that shown by Chapin et al. in U.S. Pat. No. 5,061,192. While this approach has merit, one must recognize the complex nature of fabricating the individual interconnectors as shown in FIG. 8 of the patent to Chapin et al. Note the use of a plurality of resident contact members, each requiring the painstaking application of interdigitated conductive elements 123 to the terminal ends of each contact member. Here again, cost and reliability are major deterrents to the widespread use of this design.